The Roles of Fusebox and its Interface as Part of Tessent Memory BIST Repair Solution

By Lucas Lee
Reading Time: 2 minutes

We have multiple inquires about Tessent Memory BIST to understand the Built-in-Self-Repair (BISR) architecture, specifically in regards to the fuse box and how it interfaces with the repair IP.

The fuse box is typically provided by a vendor or in-house, and holds repair information of memories of the device. Upon device power up, repair information from the fuse box is shifted along the BISR chain to the memories.

Since several vendors provide fuse boxes with varying protocols that are not common to each other, a fuse box interface would serve to describe the read and write protocols. Depending on the technology,

Siemens EDA can provide this interface. Properties pertaining to the fuse box, such as the word size, maximum number of times a fuse box can be programmed, would be described to the tool, such that the appropriate hardware, testbenches and patterns are generated. Here is an application note that details the flow requirements needed to integrate with our partner vendor’s efuse. The application note also includes a parameterized RTL template for the interface. (Access the ApplicationNote here)

There is one particularly important property that is worth pointing out. With fuse boxes typically allowing a very limited number of programming sessions, (and in many cases, just a single one), there is a property to describe the two main methods to program a fusebox: buffered and non-buffered. As the term “buffered” suggests, information is buffered during a transfer phase, before entering efuse programming phase, when the information is actually written to the efuse altogether. The goal of buffering is to limit the writing efforts. Buffering or non-buffering support depends on the specifications of the fusebox. As with the other fusebox properties, the user simply needs to have the appropriate programming_method option set during BIST insertion.

For Support and training information on Tessent Memory BIST and its BISR architecture, please refer to Support Center and Siemens’ Xcelerator Academy

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This article first appeared on the Siemens Digital Industries Software blog at