{"id":1651,"date":"2026-05-08T15:17:15","date_gmt":"2026-05-08T19:17:15","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/cicv\/?p=1651"},"modified":"2026-05-08T15:17:18","modified_gmt":"2026-05-08T19:17:18","slug":"microchips-journey-to-accelerated-verification-with-solido-additive-learning","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/cicv\/2026\/05\/08\/microchips-journey-to-accelerated-verification-with-solido-additive-learning\/","title":{"rendered":"Microchip\u2019s journey to accelerated verification with Solido Additive Learning"},"content":{"rendered":"\n

As IC applications grow in complexity and performance demands, variation-aware verification becomes essential to ensure design quality, reliability, and accuracy across operating conditions. However, traditional methods such as brute-force Monte Carlo require a large number of simulations to achieve statistically meaningful results at higher sigma levels, making them expensive and impractical for modern design cycles. The challenge grows with the iterative nature of design cycles, where designers must re-verify the design after even minor changes to ensure no new failures are introduced.  <\/p>\n\n\n\n

Solido Additive Learning addresses these challenges with an AI-driven approach that accelerates iterative verification runs by 3x to 20x. It intelligently reuses models and data from prior verification runs to reduce redundant simulations while maintaining full accuracy. As a result, re-verification cycles that typically take weeks can be completed in hours, improving engineering productivity and optimizing compute resources.<\/p>\n\n\n\n

We recently held a webinar on Solido Additive Learning and were pleased to welcome Amit Bansal, a Technical Staff Engineer at Microchip, who shared his firsthand experience using the technology.<\/p>\n\n\n\n

Microchip\u2019s design challenges<\/h2>\n\n\n\n

Amit Bansal leads analog design for FPGA products and faces the complex realities of modern chip development daily. He explained that chip design has become increasingly complex, with high gradients present across dies as technology shrinks.<\/p>\n\n\n\n

Without Solido Additive Learning, Microchip\u2019s verification process for critical designs could stretch from twenty to thirty days, making it infeasible to perform full verification checks after every design update and still meet project deadlines. Amit emphasized their need for a solution that could deliver both the accuracy and performance their design requirements demanded while saving runtime across iterations without requiring heavy engineering effort.<\/p>\n\n\n\n

Results of Microchip\u2019s implementation of Solido Additive Learning<\/h2>\n\n\n\n

Microchip ran a comprehensive evaluation of Solido Additive Learning, testing its capabilities on bandgap reference and resistive-capacitive (RC) oscillator circuits\u2014both critical to their design.<\/p>\n\n\n\n

The webinar showcased how the Microchip FPGA team in Hyderabad used Solido Additive Learning technology to speed up their 20\u201330-day iterative design process without sacrificing accuracy in their results, achieving 2x\u201320x simulation and 3x\u201319x runtime speedups across a variety of design changes and PDK updates.<\/p>\n\n\n\n

Notable results include a re-verification run across 21 PVTs on the bandgap reference circuit after a design change, which took 315 simulations and less than hour with Solido Additive Learning, compared to 1170 simulations and a nearly 3-and-a-half-hour runtime without, demonstrating a 3.7x simulation <\/strong>speedup and a 4.1x runtime <\/strong>speedup. Another experiment that changed a capacitor value and trim code on the RC oscillator circuit saw a single-PVT iterative run reduce from 300 simulations and over 14 hours, to just 15 simulations completing in 39 minutes\u2014a remarkable 20x simulation<\/strong> and 18x runtime<\/strong> speedup.<\/p>\n\n\n\n

Microchip conducted additional experiments which highlighted significant performance enhancements by using Solido Additive Learning, including:<\/p>\n\n\n\n