User2User is our annual user conference that brings together engineers and designers for keynotes, technical sessions, and direct access to our technical teams. It’s a chance to learn, share, and connect with peers who are working through the same challenges you are.<\/p>\n\n\n\n
This year’s North America event takes place on April 28, 2026 at the Santa Clara Marriott in Santa Clara, CA. The Solido Custom IC track features Intel<\/strong>, NVIDIA<\/strong>, Microsoft<\/strong>, and STMicroelectronics<\/strong> sharing their real-world experiences using AI-powered Solido tools for custom IC design, offering practical perspectives on how these solutions are being applied in production environments.<\/p>\n\n\n\n If you work in custom IC design and want to hear directly from teams already using these tools, these sessions will be worth your time.<\/p>\n\n\n\n This session discusses the challenges of verifying modern standard cell libraries, and presents how groups like the Intel Production Library team can use Solido Worst-Case Yield Solver, a batch flow utilizing Solido Design Environment high-sigma technology, to automate and accelerate verification at scale for massive standard cell libraries. This flow makes it possible to achieve brute-force accurate, variation-aware 6+ sigma verification for over a million netlists in less than a week, optimizing engineering effort and production timelines.<\/p>\n\n\n\n This session discusses a collaboration between NVIDIA and Siemens EDA to integrate a rigorous, reliable, and scalable solution for quick Liberty QA and delivery through the Solido Characterization Suite. This combines a curated, API-driven flow for NVIDIA-specific designs, timing model comparison across revisions using Solido Analytics Compare, and efficient discrepancy reporting using Solido Analytics Validate, accelerating IP integration across large design teams and diverse IP portfolios.<\/p>\n\n\n\n This session discusses how Microsoft’s AI and high-performance compute silicon programs manage large volumes of IP delivered in multiple interdependent views, where multi-view inconsistencies and unintended revision changes can evade local scripts and surface late during SoC integration, creating debug churn and schedule risk. Microsoft adopted a trust-but-verify methodology with Solido IP Validation Suite combining format-aware integrity checks, cross-view consistency validation, and revision delta analysis to turn IP quality into a repeatable, auditable gate before handoff to SoC consumers.<\/p>\n\n\n\n This session details how STMicroelectronics introduced a batch verification methodology using Solido Library Verifier, driven by an in-simulator AI engine for high-sigma yield verification with SPICE accuracy. By combining this next-generation yield solver, SPICE simulator, and Additive AI technology, STMicroelectronics achieved 7x\u201312x speedups, resulting in months of time savings.<\/p>\n\n\n\n2:00 PM \u2013 2:20 PM | Technical breakout session #1<\/strong>
Intel: Achieving unprecedented throughput for large-scale library verification with a Solido AI-powered batch flow<\/strong>
Presented by Randil Gajasinghe, standard cell design engineer, Intel<\/strong><\/h4>\n\n\n\n2:30 PM \u2013 2:50 PM | Technical breakout session #2<\/strong>
NVIDIA: Scalable and dynamic liberty verification for diverse IP<\/strong>
Presented by Eric Hsu, senior circuit design methodology staff, NVIDIA<\/strong><\/h4>\n\n\n\n3:00 PM \u2013 3:20 PM | Technical breakout session #3
Microsoft: Trust but verify for IP handoff: IP validation at scale across design views and revisions
Presented by Martin Sanchez, senior director, IP program management office, Microsoft<\/strong><\/h4>\n\n\n\n3:30 PM \u2013 3:50 PM | Technical breakout session #4<\/strong>
STMicroelectronics: Advanced high-sigma standard cell yield verification methodology using AI-powered Solido Library Verifier<\/strong>
Presented by Rohit Kumar Gupta, senior member of technical staff, STMicroelectronics and Neel Natekar, senior product manager, Siemens EDA<\/strong><\/h4>\n\n\n\n