{"id":1586,"date":"2026-03-16T16:41:01","date_gmt":"2026-03-16T20:41:01","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/cicv\/?p=1586"},"modified":"2026-03-27T09:04:44","modified_gmt":"2026-03-27T13:04:44","slug":"multi-die-verification-the-chiplet-simulation-challenge","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/cicv\/2026\/03\/16\/multi-die-verification-the-chiplet-simulation-challenge\/","title":{"rendered":"Multi-die verification: the chiplet simulation challenge"},"content":{"rendered":"\n

The shift towards chiplet-based architectures has fundamentally changed how we verify integrated circuits. When multiple dies, potentially from different vendors and different process nodes, come together in a single package, traditional simulation approaches fall short.<\/p>\n\n\n\n

The simulation challenge breaks down into three main areas:<\/p>\n\n\n\n

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  1. Different process nodes<\/strong>
    Multi-die systems often combine chiplets built on different process nodes. A chip designer might pair a 3nm node compute die with a 7nm I\/O die and HBM chiplet in 1\u03b1 (1-alpha) nm node, for instance. This creates an immediate verification problem: you need SPICE-accurate simulation across different PDKs simultaneously. The integrator must verify cross-sections between these disparate technologies and not just rely on interface IP specifications or connectivity checks, ensuring they work together despite being designed with different foundry tools and models.

    <\/li>\n\n\n\n
  2. Signal integrity across boundaries<\/strong>
    Transceivers serve as the critical gateway between chiplets and external memory. But verifying these links requires accounting for the complete signal path: through the die itself, through interposers, across package substrates, and onto the board. Each interface introduces its own challenges such as crosstalk, distortion, power, noise, jitter, etc.\u00a0For final signal integrity signoff, you need to verify the entire channel, including receiver equalization to ensure an open eye that is compliant with specifications.\u00a0

    <\/li>\n\n\n\n
  3. Mixed-signal complexity<\/strong>
    Multi-protocol I\/Os and SerDes PHYs blend analog and digital circuitry across multiple power domains. These aren’t purely digital blocks you can verify with standard logic simulation, nor purely analog circuits amenable to simple SPICE runs. They require mixed-signal verification that can handle both domains simultaneously and across the complete die surface.\u00a0These communication PHYs directly impact overall chip power, performance, and area (PPA), so getting them right is critical for tape-out.\u00a0<\/li>\n<\/ol>\n\n\n\n

    The verification engineer\u2019s reality<\/strong><\/h2>\n\n\n\n

    With all of this in mind, verifying a complete die-to-die I\/O channel from end to end presents a massive challenge with both feasibility and accuracy within integration schedules. Transceivers are critical gateways at die boundaries, whether designed with a source-synchronous clock forwarding or a clock recovery scheme for high-speed data transmission and reception. This applies to any communication protocol such as DDR, HBM, PCIe, CCIX, CXL, SATA, USB, etc., for which PHY-based IP are required. <\/p>\n\n\n\n

    Further, PHY designs are built with analog components interlaced with digital logic, and multi-voltage domains. Increasing parasitics and variability with advancing process nodes dictates the need for variation-aware and high-capacity simulation technologies. This in fact applies to all analog components on the die such as PLLs, clock tree paths, voltage regulators etc., that need to adhere to stringent specifications. <\/p>\n\n\n\n

    Verification engineers need\u00a0to\u00a0design to\u00a0SPICE-level accuracy\u00a0that\u00a0accounts for\u00a0intended\u00a0signal\u00a0effects,\u00a0as well as unintended ones like\u00a0crosstalk\u00a0and\u00a0coupling, power\u00a0supply\u00a0fluctuations\u00a0and noise\u00a0and\u00a0temperature variations. Jitter budgets need to be met\u00a0for clocking IP, where\u00a0random and deterministic\u00a0jitter\u00a0of\u00a0components within need to be accurately\u00a0quantified.\u00a0All of\u00a0this needs to be done in\u00a0a timely\u00a0fashion\u00a0to\u00a0enable design\u00a0iterations\u00a0for circuit robustness\u00a0and\u00a0final\u00a0IP\u00a0signoffs\u00a0to achieve\u00a0first-time-right (FTR)\u00a0tapeouts\u00a0in a\u00a0competitive\u00a0semiconductor market.\u00a0\u00a0\u00a0<\/p>\n\n\n\n

    The Solido approach to multi-die verification<\/strong> <\/h2>\n\n\n\n

    Meeting all these requirements simultaneously is where many existing verification flows struggle, and where the choice of simulation toolset becomes critical. Solido Simulation Suite addresses these challenges through integrated capabilities designed with multi-die verification in mind: <\/p>\n\n\n\n