{"id":1205,"date":"2025-06-16T11:56:28","date_gmt":"2025-06-16T15:56:28","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/cicv\/?p=1205"},"modified":"2026-03-27T09:04:35","modified_gmt":"2026-03-27T13:04:35","slug":"meet-the-solido-custom-ic-team-at-dac-2025","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/cicv\/2025\/06\/16\/meet-the-solido-custom-ic-team-at-dac-2025\/","title":{"rendered":"Meet the Solido Custom IC Team at DAC 2025"},"content":{"rendered":"\n

The Solido Custom IC (CIC) team is gearing up for an exciting presence at DAC 2025, where visitors will discover our innovative AI solutions that are transforming the custom IC landscape. Join us from June 23-25 in San Francisco to experience firsthand how our advanced AI-powered tools are revolutionizing design and verification workflows.<\/p>\n\n\n\n

At the Siemens EDA booth #2611, our team will be on site to guide you through an exciting interactive demo experience where you can explore our latest AI innovations in action.<\/p>\n\n\n\n

In addition to our demos, we will be hosting informative panels, technical presentations, and poster sessions featuring real-world applications and customer success stories. These sessions provide valuable insights into practical AI-driven approaches that can enhance design cycles, improve verification quality, and optimize performance for your custom IC projects.<\/p>\n\n\n\n

We have compiled a comprehensive overview of our activities at DAC, detailing when and where you can connect with our team and learn more about our innovative solutions.<\/p>\n\n\n\n

DAC Day 1: June 23<\/strong><\/h2>\n\n\n\n

Panels & Presentations with Amit Gupta<\/strong><\/h3>\n\n\n\n

Join Amit Gupta, Vice President and General Manager of Solido CIC and Siemens EDA AI, as he shares his expertise across multiple sessions on DAC’s opening day. Catch his technical presentation with Nvidia and participate in the dynamic panel discussions that follow.<\/p>\n\n\n\n

11:15am – 12:00pm
Location: DAC Pavilion, Level 2 Exhibit Hall<\/td>		Tech Talk with Nvidia: Unlocking the Power of AI in EDA<\/a><\/td><\/tr>
3:00pm – 4:00pm
Location: DAC Pavilion, Level 2 Exhibit Hal<\/td>		Cooley’s DAC Troublemaker Panel<\/a><\/td><\/tr>
4:30pm – 5:15pm 
Location: 2004, Level 2<\/td>		Siemens Panel: Achieving industrial-grade AI in EDA: challenges, lessons, and opportunities<\/a><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Engineering Track Presentations<\/strong><\/h3>\n\n\n\n
10:30am – 10:45am
Location: 2010, Level 2<\/td>		Accelerating SRAM Design Cycles With Additive AI Technology (MediaTek)<\/a><\/td><\/tr>
10:45am – 11:00am
Location: 2010, Level 2<\/td>		Novel TRNG Verification with a High-Performance Simulation Methodology (Microsoft)<\/a><\/td><\/tr>
11:00am – 11:15am
Location: 2010, Level 2<\/td>		Accelerating Bandgap Reference High-Sigma Verification with Additive AI Technology (Microsoft)<\/a><\/td><\/tr>
11:45am – 12:00pm
Location: 2010, Level 2<\/td>		Advanced Verification Solutions for Communication ICs to Ensure High Quality Amid PVT Variations (THine)<\/a><\/td><\/tr>
3:45pm – 4:00pm
Location: 2010, Level 2<\/td>		Logic and SRAM Library Generation and Analysis for Digital Design Enablement (Google)<\/a><\/td><\/tr>
4:45pm – 5:00pm
Location: 2010, Level 2<\/td>		Robust Verification for Complex Liberty IP (NXP)<\/a><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Engineering Track Poster<\/strong>s<\/h3>\n\n\n\n
5:00pm – 6:00pm
Location: Poster Reception \u2013 Level 2 Exhibit Hall  <\/td>		Advanced Yield Prediction for SRAM Bitcells with Rare Defect Modeling Leveraging AI-Powered Methodology (GlobalFoundries)<\/a><\/td><\/tr>
5:00pm – 6:00pm
Location: Poster Reception \u2013 Level 2 Exhibit Hall <\/td>		Using AI to Validate Standard Cell Liberty IP Riddled with Sparse and Disparate Data (Infineon)<\/a><\/td><\/tr>
5:00pm – 6:00pm
Location: Poster Reception \u2013 Level 2 Exhibit Hall <\/td>		Accelerating SRAM Design Cycles With Additive AI Technology (MediaTek)<\/a><\/td><\/tr>
5:00pm – 6:00pm
Location: Poster Reception \u2013 Level 2 Exhibit Hall<\/td>		Novel TRNG Verification with a High-Performance Simulation Methodology (Microsoft)<\/a><\/td><\/tr>
5:00pm – 6:00pm
Location: Poster Reception \u2013 Level 2 Exhibit Hall <\/td>		Accelerating Bandgap Reference High-Sigma Verification with Additive AI Technology (Microsoft)<\/a><\/td><\/tr>
5:00pm – 6:00pm
Location: Poster Reception \u2013 Level 2 Exhibit Hall  <\/td>		Advanced Verification Solutions for Communication ICs to Ensure High Quality Amid PVT Variations (THine)<\/a><\/td><\/tr>
5:00pm – 6:00pm
Location: Poster Reception \u2013 Level 2 Exhibit Hall <\/td>		Logic and SRAM Library Generation and Analysis for Digital Design Enablement (Google)<\/a><\/td><\/tr>
5:00pm – 6:00pm  
Location: Poster Reception \u2013 Level 2 Exhibit Hall<\/td>		Robust Verification for Complex Liberty IP (NXP)<\/a><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

DAC Day 2: June 24<\/strong><\/h2>\n\n\n\n

Engineering Track Poster<\/strong>s<\/h3>\n\n\n\n
5:00pm – 6:00pm  
Location: Poster Reception \u2013 Level 2 Exhibit Hall<\/td>		AI-Based Trimming and Optimization for Voltage Regulators: Proven Accuracy with Wafer Data (SK hynix)<\/a><\/strong><\/td><\/tr>
5:00pm – 6:00pm  
Location: Poster Reception \u2013 Level 2 Exhibit Hall<\/td>		Automated QA for Standard Cell Libraries used in RAIN RFID Chips (Impinj)<\/a><\/strong><\/td><\/tr>
5:00pm – 6:00pm  
Location: Poster Reception \u2013 Level 2 Exhibit Hall<\/td>		Portfolio Re-characterization Using AI (NXP)<\/a> <\/strong><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Engineering Track Poster<\/strong> Gladiator Showdown<\/strong><\/h3>\n\n\n\n

5:21 – 5:28 PM
Location: Poster Reception \u2013 Level 2 Exhibit Hall<\/p>\n\n\n\n

We are proud to announce that the poster “Accelerating Chip Design with AI-Powered Additive Learning for Deep Sub-Micron Technologies” is a DAC Gladiator Poster Award finalist. We will present this innovative research in a dynamic 5-minute format, competing for the award against other finalists. Join us to learn how AI-powered additive learning is advancing chip design in deep sub-micron technologies.<\/p>\n\n\n\n

DAC Day 3: June 25<\/strong><\/h2>\n\n\n\n

Engineering Track Poster<\/strong>s<\/h3>\n\n\n\n
12:15pm\u00a0–\u00a01:15pm
Location: Poster Reception \u2013 Level 2 Exhibit Hall<\/td>		Accelerating Chip Design with AI-Powered Additive Learning for Deep Sub-Micron Technologies (Microchip)<\/a><\/strong><\/td><\/tr>
12:15pm\u00a0–\u00a01:15pm \u00a0
Location: Poster Reception \u2013 Level 2 Exhibit Hall<\/td>		Enhancements in Cell-Aware UDFM Models to Optimize the Development Flow of Custom Macros\/IP and Standard Cell Libraries (NXP)<\/a><\/strong><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

We look forward to connecting with you at DAC 2025. Whether you are interested in specific technical sessions, want to discuss your design challenges with our experts, or simply catch up on the latest developments in Solido solutions, we would love to meet you.

Stop by the Siemens EDA booth (#2611), check out our presentations and poster sessions, or reach out to your account manager to schedule a dedicated meeting. See you in San Francisco!<\/p>\n\n\n\n

<\/p>\n","protected":false},"excerpt":{"rendered":"

The Solido Custom IC (CIC) team is gearing up for an exciting presence at DAC 2025, where visitors will discover our innovative AI solutions that are transforming the custom IC landscape. <\/p>\n","protected":false},"author":110486,"featured_media":1307,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[5,1],"tags":[305,470,469,471,506],"industry":[34],"product":[235],"coauthors":[496],"class_list":["post-1205","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-events","category-news","tag-ai","tag-solido-characterization-suite","tag-solido-design-environment","tag-solido-ip-validation","tag-solido-simulation-suite","industry-electronics-semiconductors","product-solido"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/58\/2025\/06\/EDA-2025-pics-1920x1080_0005_6.jpg","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/posts\/1205","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/users\/110486"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/comments?post=1205"}],"version-history":[{"count":5,"href":"https:\/\/blogs.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/posts\/1205\/revisions"}],"predecessor-version":[{"id":1401,"href":"https:\/\/blogs.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/posts\/1205\/revisions\/1401"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/media\/1307"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/media?parent=1205"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/categories?post=1205"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/tags?post=1205"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/industry?post=1205"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/product?post=1205"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/coauthors?post=1205"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}