Heading to DAC 2025 with Thine: Advanced Verification Solutions for ICs to Ensure High Quality Amid PVT Variations

At the center of modern communication systems lies a critical component: the phase interpolator (PI). This relatively tiny component plays a crucial role in controlling sampling clock timing, making its accuracy fundamental to the entire system’s reliability and performance. However, designing and verifying these components can be challenging. Manufacturing variations in semiconductor processes can significantly impact performance, and traditional verification methods have proven to be insufficient for today’s demanding design needs.

The Bottleneck in Traditional Verification of PIs

The verification process faces three major obstacles:

• The massive size of PI circuits in communication systems
• The extensive time required for transient simulations
• The need for statistical simulations to verify manufacturing variations in semiconductor process

The Solution: AI-Powered Design Verification by Solido Simulation Suite and Solido Design Environment

In response to these challenges, THine Electronics and Siemens EDA joined forces to develop an innovative solution. The collaboration resulted in an AI-powered design verification flow that leverages two powerful tools: Solido Simulation Suite and Solido Design Environment.

The new methodology achieves a 174X reduction in design cycle time while providing comprehensive coverage across 64 PVT corners and phase interpolator code combinations. Solido Simulation Suite delivers accurate PI verification through advanced parasitic reduction techniques, while Solido PVTMC Verifier, part of Solido Design Environment, enables AI-powered variation-aware analysis to ensure reliable statistical results.

Join THine Electronics & Siemens EDA at DAC 2025

We’re delighted to announce that our paper on AI-powered verification flow for PIs has been selected for presentation at DAC 2025 in the IP Engineering track. Join us for an in-depth technical session where we will demonstrate how you can utilize Solido Simulation Suite and Solido Simulation Suite to achieve an innovative verification flow for communication systems.

Date: June 23(Mon), 2025

Location: Moscone West, Room 2010, Level 2

Time: 11:45am – 12:00pm

Speakers: Lih-Jen Hou

Discover how Solido Custom IC Solutions, including Solido Simulation Suite and Solido Design Environment, can transform your verification workflow: Solido Solutions | Siemens Software

For complete DAC 2025 conference information and registration: Design Automation Conference