{"id":3784,"date":"2026-04-13T13:26:07","date_gmt":"2026-04-13T17:26:07","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/calibre\/?p=3784"},"modified":"2026-04-13T13:26:09","modified_gmt":"2026-04-13T17:26:09","slug":"why-a-gpu-rasterizer-matters-for-computational-lithography-in-both-performance-and-precision-at-scale","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/calibre\/2026\/04\/13\/why-a-gpu-rasterizer-matters-for-computational-lithography-in-both-performance-and-precision-at-scale\/","title":{"rendered":"Why a GPU rasterizer matters for computational lithography in both performance and precision at scale"},"content":{"rendered":"\n

By Loay Hegazy, Mohamed Taher, Sherif Hammouda<\/p>\n\n\n\n

Rasterization\u2014converting continuous geometric shapes into discrete pixel grids\u2014is fundamental to computational lithography<\/a><\/strong>. In optical proximity correction (OPC) and mask synthesis workflows, rasterization must achieve both speed and nanometer-scale precision.<\/p>\n\n\n\n

Watch now (3 min): Reshaping the lithography industry with Calibre Advanced OPC Solutions<\/a><\/strong><\/p>\n\n\n\n

Traditional CPU-based rasterizers process workloads sequentially, creating a bottleneck in the design cycle. GPUs offer massive parallelism, but applying them to lithography rasterization presents challenges: maintaining floating-point precision, preserving sub-pixel connectivity and handling irregular memory access patterns.<\/p>\n\n\n\n

Based on originally presented at SC25<\/strong><\/a>, the international conference for high performance computing, networking, storage and analysis, we describe a GPU rasterizer designed specifically for computational lithography, and present benchmark results and practical implications for mask synthesis workflows.<\/p>\n\n\n\n

Fractional pixel coverage: the lithography rasterization challenge<\/h2>\n\n\n\n

Rasterization in graphics typically uses a binary coverage model: pixels are either fully covered or not. This suffices for visual rendering, but lithography demands fractional pixel coverage (figure 1). Light intensity and resist behavior depend on the precise area of each pixel occupied by a polygon\u2014a requirement that becomes critical at nanometer scales.<\/p>\n\n\n\n

\"An
Figure 1. Example of converting a polygon into a pixel-based representation through rasterization<\/figcaption><\/figure>\n\n\n\n

Consider a polygon edge that crosses a pixel diagonally. A binary model would assign the pixel fully to one polygon or the other, introducing a 50% error in coverage. A fractional model computes the exact overlap area, capturing the physics of the lithographic process. For thin features and sub-wavelength structures, this precision directly impacts manufacturability.<\/p>\n\n\n\n

The challenge is computing fractional coverage for billions of pixels while maintaining connectivity between sub-pixel geometries\u2014ensuring that thin features do not fragment into disconnected regions during pixelization.<\/p>\n\n\n\n

GPU rasterizer algorithm: five-stage parallel architecture<\/h2>\n\n\n\n

Our GPU rasterizer decomposes the problem into five sequential stages, each designed for parallel execution on thousands of GPU threads.<\/p>\n\n\n\n

Stage 1: Initialization and polygon assignment<\/strong><\/p>\n\n\n\n

The algorithm begins by zeroing all pixels in the output grid and reserving shared memory for polygon data. Polygons are assigned to thread blocks based on spatial location, enabling simultaneous processing of multiple polygons across the GPU.<\/p>\n\n\n\n

A coarse-grained bounding box approach identifies which polygons might overlap specific regions. This pruning step is essential: it prevents threads from evaluating pixel-polygon pairs that cannot possibly intersect, reducing wasted computation.<\/p>\n\n\n\n

Stage 2: Bounding box calculation<\/strong><\/p>\n\n\n\n

For each assigned polygon, a precise bounding box is computed from vertex coordinates. This defines the minimal region requiring detailed rasterization, limiting computation to relevant pixels.<\/p>\n\n\n\n

The bounding box approach introduces a tradeoff: it may include extra area outside the polygon (as shown in figure 2), creating a collision zone that requires additional processing. However, this overhead is acceptable because it enables efficient spatial pruning and coalesced memory access.<\/p>\n\n\n\n

\"A
Figure 2. Example of computing bounding box for a polygon<\/figcaption><\/figure>\n\n\n\n

Stage 3: Thread-pixel allocation<\/strong><\/p>\n\n\n\n

GPU threads are dynamically allocated to individual pixels or small groups of pixels within each polygon’s bounding box. This fine-grained parallelism is the key to GPU efficiency. Each thread independently determines its pixel’s contribution to coverage, with minimal inter-thread synchronization.<\/p>\n\n\n\n

A fixed-size thread block processes pixels in segments, scanning the bounding box in a coalesced memory access pattern. For example, a 1D thread block of 4 threads processes the first 4 pixels, then shifts to the next 4, continuing until the entire bounding box is scanned (figure 3). This pattern maximizes memory bandwidth utilization, a critical factor for GPU performance.<\/p>\n\n\n\n

\"A
Figure 3. Example on output grid for rasterization of a simple L-shape using a block of threads<\/figcaption><\/figure>\n\n\n\n

Stage 4: Pixel classification<\/strong><\/p>\n\n\n\n

For each pixel, the algorithm classifies it as inside, outside, or on the boundary of the polygon:<\/p>\n\n\n\n