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- Long runtimes<\/strong> \u2013 As design rules grow in complexity, verification runtimes increase exponentially.<\/li>\n\n\n\n
- Incomplete layouts<\/strong> \u2013 Many designs are finalized in stages, making full verification impractical until later in the design process.<\/li>\n\n\n\n
- Debug inefficiencies<\/strong> \u2013 Global rule violations take longer to trace and correct due to their non-localized nature.<\/li>\n<\/ul>\n\n\n\n
The impact? Teams face significant delays in debugging and validation, often leading to extended tape-out timelines and increased resource consumption.<\/p>\n\n\n\n
The solution: A Shift left approach with Calibre nmDRC Recon<\/strong><\/h2>\n\n\n\n
Recognizing these challenges, Siemens introduced Calibre nmDRC Recon<\/strong><\/a>, a revolutionary shift left verification strategy designed to perform early, localized rule checks, reducing debug times and resource consumption. Instead of waiting for full-layout readiness, nmDRC Recon enables designers to catch and correct major layout violations much earlier in the design cycle.<\/p>\n\n\n\n
![\"Graphs](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/50\/2025\/02\/Figure-1-nmDRC-Recon-1024x390.jpg\")
Showing the difference in runtimes and memory usage between regular nmDRC and nmDRC Recon. The improvements from 4 and 15 times for runtime and between 2 18 times for memory usage across various designs.<\/figcaption><\/figure>\n\n\n\n <\/p>\n\n\n\n
One of the key advantages of nmDRC Recon is its ability to accelerate debug cycles<\/strong>. By running only relevant, local-scope checks, it significantly speeds up the verification process, allowing designers to identify and address errors more efficiently.<\/p>\n\n\n\n
Another major benefit is the reduction in compute load<\/strong>. Instead of processing an entire design at once, nmDRC Recon selectively verifies specific design components, which helps minimize hardware requirements. This makes it a practical solution for teams working with limited computing resources.<\/p>\n\n\n\n
Finally, nmDRC Recon enhances targeted error detection<\/strong> by pinpointing violations closer to their root cause. This minimizes unnecessary iterations and helps designers focus on resolving key issues without being overwhelmed by unrelated errors. The result is a more streamlined and efficient verification process that ultimately accelerates time to tape-out.<\/p>\n\n\n\n
How Calibre nmDRC Recon streamlines and accelerates DRC verification<\/strong><\/h2>\n\n\n\n
Calibre nmDRC Recon focuses on local verification first, meaning it runs checks that don\u2019t require deep hierarchical analysis or connectivity data. This reduces runtime and hardware usage significantly. Here\u2019s how designers can leverage it:<\/p>\n\n\n\n
1. Early-stage verification with localized checks<\/strong><\/p>\n\n\n\n
Traditional DRC runs all rules across the full layout, even when only partial data is available. Instead, nmDRC Recon focuses on local scope violations\u2014those not dependent on hierarchy or connectivity. This enables early detection of gross errors in:<\/p>\n\n\n\n
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- Floorplanning<\/li>\n\n\n\n
- Cell placement<\/li>\n\n\n\n
- Chip finishing<\/li>\n<\/ul>\n\n\n\n
By resolving these issues sooner, designers avoid compounded errors later in the flow.<\/p>\n\n\n\n
2. Customizable rule selection<\/strong><\/p>\n\n\n\n
Not all DRC rules are equal in complexity. With Calibre nmDRC Recon, teams can modify default behavior by enabling or disabling specific rule types. For example:<\/p>\n\n\n\n
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- Designers can run onlychecks related to modified layers, focusing debugging efforts on recent changes.<\/li>\n\n\n\n
- Certain checks can be prioritized or deferred, allowing designers to balance speed and thoroughness.<\/li>\n<\/ul>\n\n\n\n
This flexibility ensures that teams only run the rules that matter at each design stage.<\/p>\n\n\n\n
3. Accelerating full verification with connectivity-aware checks<\/strong><\/p>\n\n\n\n
Even after resolving local violations, some checks\u2014such as electrostatic discharge (ESD), latch-up, and multi-patterning rules\u2014require full connectivity data. This is where Calibre nmLVS Recon SI comes in <\/strong>(quick video available here! Watch: Calibre nmLVS Recon<\/strong><\/a>)<\/p>\n\n\n\n
By performing fast connectivity analysis and pinpointing shorted nets early, Calibre nmLVS Recon SI prevents unnecessary DRC slowdowns and debug cycles, ensuring that later iterations are efficient and meaningful.<\/p>\n\n\n\n
Real-world impact of Calibre nmDRC Recon<\/strong><\/h2>\n\n\n\n
One of our customers was facing significant DRC verification bottlenecks in their IC designs, adopted Calibre nmDRC Recon to enhance productivity. Their approach:<\/p>\n\n\n\n
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- Integrated nmDRC Recon at the floorplan and physical implementation stages.<\/li>\n\n\n\n
- Focused on early detection of power-ground shorts.<\/li>\n\n\n\n
- Achieved significant runtime reductions compared to traditional methods.<\/li>\n<\/ul>\n\n\n\n
![\"Using](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/50\/2025\/02\/Fig-2-DRC-flow-1024x214.jpg\")
Using faster Calibre DRC Recon iterations, designers can reduce overall TAT by up to 5X.<\/figcaption><\/figure>\n\n\n\n <\/p>\n\n\n\n
You can read more about Calibre nmDRC Recon in our recent technical paper now available The power of shift-left DRC verification with Calibre nmDRC Recon<\/strong><\/a><\/p>\n\n\n\n
The future of IC design verification<\/strong><\/h2>\n\n\n\n
- Incomplete layouts<\/strong> \u2013 Many designs are finalized in stages, making full verification impractical until later in the design process.<\/li>\n\n\n\n