{"id":2841,"date":"2024-04-10T12:11:38","date_gmt":"2024-04-10T16:11:38","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/calibre\/?p=2841"},"modified":"2026-03-26T16:23:18","modified_gmt":"2026-03-26T20:23:18","slug":"how-to-verify-well-layer-connectivity-with-soft-checks","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/calibre\/2024\/04\/10\/how-to-verify-well-layer-connectivity-with-soft-checks\/","title":{"rendered":"How to verify well layer connectivity with soft checks"},"content":{"rendered":"\n

By Terry Meeks<\/p>\n\n\n\n

In the landscape of modern IC chip verification, ensuring the connectivity from diffusion layers to well regions is critical for the proper functioning of integrated circuits (ICs). If power or ground are not connected correctly, the chip will fail. Soft checks, a specific type of Electrical Rules Check (ERC), play a pivotal role in examining this connectivity, preventing conflicts, and ensuring the integrity of power and ground nets. Let\u2019s delve into the nuances of soft checks and the methodologies for efficient detection and debugging.<\/p>\n\n\n\n

Unpacking the notion of “soft checks”<\/h2>\n\n\n\n

A “soft check” refers to an ERC that scrutinizes the connectivity from the diffusion layers to the well (substrate) regions of the IC design. Referred to as \u201cstamping,\u201d soft connectivity connects an upper layer to a lower layer without allowing the connectivity from the lower layer to affect other upper layer polygons. A soft check evaluates this soft connection to identify and report any conflicting shapes. The primary objective of soft checks is to ensure that all of the well regions are connected to power or ground through the metal layers to the diffusion taps, eliminating device connections through the well layers.<\/p>\n\n\n\n

Understanding well layer connectivity<\/h2>\n\n\n\n

The importance of well layer connectivity is often underestimated in IC design. Some digital designs may simplify connectivity verification by having one power and one ground voltage. Many modern designs, especially analog ones, involve multiple voltages, making well connectivity more complex. Additionally, as process nodes shrink, analog effects become more prominent, adding complexity to well layer connectivity modeling.<\/p>\n\n\n\n

Connectivity between layers in an IC layout is typically determined by assigning the same net identifier when the polygons in those layers touch or overlap. This connectivity must be a two-way relationship that connects the polygons in both directions (figure 1).<\/p>\n\n\n\n

\"Diagram
Figure 1. Top-down view of connectivity between layers. The top illustration shows two polygons that do not interact, so these polygons are not connected. In the lower illustration, the three shapes interact and are all connected.<\/em><\/figcaption><\/figure>\n\n\n\n

When there is an intermediate connecting layer like a contact or via, the behavior of the connect function is a little bit different.\u00a0In that case, the three layers must all overlap at the same location, as shown in figure 2.<\/p>\n\n\n\n

\"Diagram
Figure 2. Connectivity with an intermediate layer as seen from a side view and top view. The upper illustrations show that the Metal1 polygon touches the Metal2 polygon but does not overlap the Via1 polygon, so the shapes are not connected. In the lower illustrations, the three shapes overlap in the same location and are connected as the same net ID.<\/figcaption><\/figure>\n\n\n\n

Soft connectivity from diffusion to well layers<\/h2>\n\n\n\n

Well layers should not be used to conduct signals due to their lower doping concentration. Soft connectivity, often termed “stamping,” creates a one-way connection from an upper layer to a lower well layer, avoiding high-resistance connections.<\/p>\n\n\n\n

Soft connectivity from diffusion layers to well layers involves a direct, two-layer event. N+ and P+ implanted diffusion regions within NWell and PWell regions, respectively, conduct current. In figure 3, the connection shown on the left side has Metal1 (named Gnd) connect through a contact to a diffusion region over a like-biased well region (N+ to NWell, or P+ to PWell), which is known as a tap diffusion. The metal layer closest to the tap diffusion shapes connects through a contact opening layer, situated above the diffusion layer. This connection doesn’t directly participate in connecting to the well but contributes to the connectivity of the diffusion layer.<\/p>\n\n\n\n

The Metal1 shape on the right (which is not on the Gnd net) connects to another contact, and to a different tap diffusion shape. However, because the Gnd net is selected to stamp the Rwell shape, this other net is in conflict and is reported as an error by the soft check.<\/p>\n\n\n\n

\"Diagram
Figure 3. Cross-section view of well connectivity error.<\/figcaption><\/figure>\n\n\n\n

Performing soft checks<\/h2>\n\n\n\n

Soft checks are executed as part of the layout vs. schematic (LVS) extraction flow. The rules file for LVS must include soft check statements, and the results are typically reported in the LVS extraction report and a separate results database. For example, in Calibre\u00ae nmLVS\u2122<\/strong><\/a> reporting, soft check results are provided in a Calibre results database that is readable by the Calibre RVE<\/a> <\/strong>results viewer.<\/p>\n\n\n\n

Debugging soft check errors<\/h2>\n\n\n\n

Debugging a soft check involves understanding what the error is reporting\u2014the attempt to apply more than one net from the upper layer to the lower well layer. There are two primary steps in resolving soft check errors:<\/p>\n\n\n\n

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  1. Review upper layer connectivity: Analyze the connectivity of the upper layer, depending on the type of well involved (NWell or PWell). Correct any unconnected (open) nets.<\/li>\n\n\n\n
  2. Examine lower layer separation: If upper layer connectivity is correct, investigate issues in lower layer separation. Ensure well shapes are appropriately broken up into uniquely named regions using a marker layer.<\/li>\n<\/ol>\n\n\n\n

    Using Calibre RVE for debugging<\/h2>\n\n\n\n

    The Calibre RVE<\/strong><\/a> results viewer provides a rich set of features to facilitate efficient debugging of soft check errors. It offers detailed information on conflicting shapes, enabling designers to understand the relationship of shapes to the design. The viewer allows for easy examination of upper and lower layer connectivity and provides visualization tools for better comprehension.<\/p>\n\n\n\n

    Figure 4 shows the expanded detail displayed in the Calibre RVE results viewer. The tree view at top includes the following attributes:<\/p>\n\n\n\n