{"id":2406,"date":"2022-03-16T11:42:55","date_gmt":"2022-03-16T15:42:55","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/calibre\/?p=2406"},"modified":"2026-03-26T16:21:37","modified_gmt":"2026-03-26T20:21:37","slug":"ease-on-down-the-roadwhy-ease-of-use-is-the-next-big-thing-in-eda-and-how-we-get-there","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/calibre\/2022\/03\/16\/ease-on-down-the-roadwhy-ease-of-use-is-the-next-big-thing-in-eda-and-how-we-get-there\/","title":{"rendered":"Ease on down the road\u2026why \u201cease of use\u201d is the next big thing in EDA, and how we get there"},"content":{"rendered":"\n

Ease of use is an important issue when enhancing product functionality and introducing new technology. Calibre Design Systems considers ease of use a critical design factor, which is reflected in the multiple strategies and technologies we use to implement and improve ease of use throughout the Calibre nmPlatform.<\/em><\/p>\n\n\n\n

Electronic design automation (EDA) is all about simplifying and automating the process of ensuring your IC design can be turned into working silicon that delivers the performance and product life the market expects. EDA tools and technology are the crucial foundation of the semiconductor industry\u2019s advances over the years. Moore\u2019s law, as well as innovations like finFETs, multi-patterning, and 3D ICs, wouldn\u2019t even be possible without the automation of the analysis, optimization, and verification processes that must happen to create the \u201cdesign to silicon\u201d flow.<\/p>\n\n\n\n

But just automating a process doesn\u2019t necessarily make it easier to use. Oh, it might speed things up, compared to visual design inspections and tedious manual layout corrections, but ease of use is as much a deliberate design goal as speed and accuracy. The team behind the Calibre nmPlatform includes ease of use as one of the critical criteria when considering ways to enhance and expand our portfolio of industry-leading verification solutions. We also recognize that ease of use is an iterative and progressive process that evolves as the tools and processes change.<\/p>\n\n\n\n

Okay, but what does ease of use mean to the designers and engineers who use Calibre tools? Well, that\u2019s the whole idea\u2014looking at functionality from the user\u2019s perspective, and thinking about what really makes a difference to design teams during their IC design and verification flows. It means talking to those teams, getting their insights and needs and \u201cwish lists,\u201d and taking all of that feedback into consideration when evaluating our platform and the individual tools.<\/p>\n\n\n\n

For example, the design rule checking (DRC) process is a major percentage of the design verification flow. But, without DRC compliance, designs cannot be taped out and sent to the foundry for manufacturing. To minimize the impact of DRC batch runs on the schedule and resources of a design team, we constantly improve processing speed and memory resource use across design styles and process nodes. We also provide complementary functionality, such as pattern matching, automated waiver processing, and multi-patterning verification, that support and streamline complex DRC. And of course, ensuring Calibre performs and scales as well in the cloud as it does onsite helps companies acquire the necessary resources when physical investment on premise simply isn\u2019t an option.<\/p>\n\n\n\n

But a Calibre nmDRC batch run is still always going to require a significant chunk of time and compute resources in a verification flow, no matter how fast and efficiently it runs. So we examined the entire DRC process, and asked, \u201cWhat if designers could eliminate some errors earlier in the design flow?\u201d That train of thought led to the introduction of several innovative tools that provide design teams with early design exploration and verification functionality that accelerates DRC closure, reduces the overall schedule, and provides designers more time to focus on meeting power, performance, and area goals.<\/p>\n\n\n\n

The Calibre nmDRC Recon tool provides SoC designers with the ability to run selective full-chip verification early in the design implementation and integration stages, helping them find and correct systemic errors, like off-grid block placements or routing violations, with faster runtimes and simpler debug. Minimizing full DRC batch runs early in the design cycle can add up to significant savings in overall schedule time.<\/p>\n\n\n\n

Meanwhile, the Calibre RealTime Custom and Calibre RealTime Analog tools enable on-demand Calibre signoff DRC within the design and implementation environments, allowing designers to perform targeted DRC checks on the layouts and receive immediate Calibre DRC feedback. With that information, they can quickly apply and verify fixes with Calibre confidence that the results are DRC-clean.<\/p>\n\n\n\n

Those are just a couple of examples focusing on the DRC flow, but the same attention is paid to every part of the design verification and optimization flow, and to every tool in the Calibre portfolio. Constant optimization and innovation are key to improvements in ease of use.<\/p>\n\n\n\n

Ease of use isn\u2019t just about performance, though\u2014it\u2019s also connected with how easy and intuitive it is to use a tool. Developing and enhancing tool GUIs to provide quick selection of check and run options and requirements lets designers focus on the task at hand, rather than spending time writing code. And, because Calibre tools are integrated with a wide variety of design and implementation environments, we strive to ensure consistent interfaces across all integrations so design teams can easily switch between different tools as needed.<\/p>\n\n\n\n

Interested in learning more about how Calibre Design Solutions constantly looks for ways to improve ease of use for the Calibre nmPlatform? Here are some links you might like to explore\u2026<\/p>\n\n\n\n

Visiting our product pages<\/a> is a great place to start! You can browse the entire range of Calibre Design software solutions, or hone in on a particular topic by browsing the resource library link at the top of each product family page.<\/p>\n\n\n\n

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If you want to get right to the nitty-gritty details, here are some recommended resources discussing how the Calibre nmPlatform is providing an improved ease of use experience in the physical verification flow:<\/p>\n\n\n\n

Technical papers:<\/strong><\/p>\n\n\n\n

New approaches to physical verification closure and cloud computing come to the rescue in the EUV era<\/a><\/p>\n\n\n\n

Automated post-processing of DRC errors improves debugging productivity<\/a><\/p>\n\n\n\n

Data integrity checks save time and resources in parallel IC design flows<\/a><\/p>\n\n\n\n

Custom integrity checks find early IC design implementation errors<\/a><\/p>\n\n\n\n

Advanced symmetry checking in IC layout design and verification<\/a><\/p>\n\n\n\n

Construct by correction with selective verification enhances productivity<\/a><\/p>\n\n\n\n

EDA in the cloud\u2014Now more than ever<\/a><\/p>\n\n\n\n

Videos:<\/strong><\/p>\n\n\n\n

Calibre physical verification – Solutions for your next node<\/a><\/p>\n\n\n\n

Accelerate PV closure using Calibre RealTime Digital DRC<\/a><\/p>\n\n\n\n

Enhanced P&R designer productivity and design quality<\/a> Calibre RealTime platform overview<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

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