<\/p>\n New packaging technologies and processes are getting a lot of attention these days. Wafer-level packaging (WLP) is one promising \u201cMore than Moore\u201d technology that enables higher form factor and improved performance compared to traditional system-on-chip (SoC) designs. One of the advantages of WLP over 2.5D and 3D integrated circuit designs is that WLP doesn\u2019t require through silicon vias (TSVs), which are expensive, and tend to cause mechanical and thermal reliability issues. On the flip side, the package design and verification process suddenly becomes much more complex.<\/p>\n Design and verification flows for SoCs are well-established, and they\u2019ve been used by designers for decades. For a given process technology, a foundry provides a set of design rules that SoC designs must comply with, to ensure the SoC can be manufactured by the foundry. Electronic design automation (EDA) companies provide automated physical verification flows to help designers ensure their SoC designs satisfy these rules, along with similar automated flows for connectivity checking, parasitic extraction, post-layout simulation, etc. As a technology matures, the foundry eventually supplies designers with a fully-developed SoC process design kit (PDK) for the process node. Designers use this PDK in conjunction with a set of EDA tools and processes (reference flow) to deliver a design that is guaranteed to be compliant with the foundry design requirements and manufacturing process.<\/p>\n Package design and verification flows? Let\u2019s just say they\u2019re a little more\u2026casual. Many package designs are assembled manually. They typically have very little in the form of formal sign-off requirements that accompany the package design, other than a textual document describing the intended design rules. Consequently, the EDA tool functionality for package design and verification has historically been much simpler as well.<\/p>\n However, because WLP manufacturing occurs at the \u201cwafer level,\u201d it incorporates mask generation, similar to the SoC manufacturing flow. Now solid package design and verification flows must be in place so the designer can ensure manufacturability of the FOWLP by the foundry or OSAT company. Similar to the PDKs used for an SoC, the foundry or OSAT now needs to provide package designers with some form of an assembly design kit (ADK) that brings together the chip and package design environments.<\/p>\n Mentor is at the forefront of this evolution with innovative EDA functionality that helps bridge the gap between IC and package verification.<\/p>\n If you\u2019d like more details about the Mentor solution, check out our white paper, Crossing the Chasm: Bringing SoC and Package Verification Together with Calibre 3DSTACK<\/a><\/p>\n![\"\"](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/50\/2017\/04\/Package-it-up_banner.jpg\")
<\/a><\/p>\n