Resetting Expectations on Multi-Patterning Decomposition and Checking

By David Abercrombie, Mentor Graphics Some common misconceptions about multi-patterning processes and just how they…

Design Rule Checking for Silicon Photonics

By Ruping Cao, Mentor Graphics Verifying silicon photonics designs requires new techniques, like equation-based DRC…

MEMS Technology and Manufacturing on the Microscale

By Carey Robertson and Khaled AbouZeid, Mentor Graphics Designers incorporating MEMS devices into high-volume CMOS…

Electrical Overstress Detection and Debugging

By Dina Medhat, Mentor Graphics Automated voltage propagation provides an accurate way to detect and…

Case Studies in P&R Double Patterning Debug: Part Two

David Abercrombie continues his expert advice to P&R and chip finishing engineers on understanding and…

Case Studies in Double-Patterning Debug: Part One

By David Abercrombie, Mentor Graphics Multi-patterning errors in P&R layouts can be intricate, and their…

The Changing (and Challenging) IC Reliability Landscape

By Matthew Hogan, Mentor Graphics Reliability issues have gone way beyond DRC and LVS verification……

The Fill Ecosystem Evolves Again

By Jeff Wilson, Mentor Graphics At 20nm, new fill constraints drive up the time and…

Extraction Challenges Grow in Advanced Nanometer IC Design

By Carey Robertson, Mentor Graphics The Calibre xACT platform is a new type of extraction…