DAC in December?? A Review of Calibre Design Solutions at DAC 2021

Did it feel a bit weird to be submitting research papers for DAC 2022 while packing to go to DAC…

Is there a quick and easy way to calculate P2P resistance or current density between any two coordinates in my IC design layout?

By Li Li Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point…

The “next” technology node: ready or not, here it comes

By Shelly Stalnaker For years, decades even, the semiconductor industry has lived by the process node, which was originally named…

Physical design engineers…Learn the secret to generating signoff fill in P&R and accelerating your tapeouts

By Srinivas Velivala Place and route (P&R) engineers are always on the lookout for ways to optimize their design flows…

Stronger together! Context-aware SPICE simulation combines the strengths of static and dynamic verification for faster, more precise full-chip ESD verification

By Neel Natekar Running dynamic simulations for full-chip ESD verification of ICs has become increasingly difficult (and in some cases,…

Package verification just took a big step forward…

By Armen Asatryan and John Ferguson Over a decade ago, Calibre Design Solutions moved early into defining and building physical…

Coding for maximum performance and efficiency

A great software program does much, much more than just execute routines. It also optimizes the use of CPU resources…

Calibre Design Solutions takes a look back at 2021

Okay, is everyone ready for an end-of-year wrapup? It’s certainly been an eventful 2021 for Calibre Design Solutions, even if…

Calibre Design Solutions at Samsung SAFE Forum: technology leadership through innovation, intelligence, and integration

Since 2018, Samsung Foundry has operated their foundry ecosystem program, called SAFE™ (Samsung Advanced Foundry Ecosystem), to ensure deep collaboration…