By Wael ElManhawy – Mentor, A Siemens Business
You want to support your customer who is using a new technology, but they don’t have enough designs to provide real design data for all layers to do early testing for their core DRC decks and detect problematic lithographic patterns? Wael ElManhawy explains how the Calibre Layout Schema Generator (LSG) tool steps in to cover that gap…
As semiconductor technology continues to advance post-haste, foundries and independent device manufacturers (IDMs) are under ever-increasing pressure to ramp to volume production faster. The need for early detection of potential lithographic (litho) distortions or failures (hotspots) before tapeout is essential. This detection process is critical at all levels—from designing standard cells and small blocks, to large intellectual property (IP) and full chip layouts. But while litho fidelity is essential to the success of integrated circuit (IC) manufacturing, estimating and predicting areas of lithographic difficulty during the early stages of process technology node development has always been a challenge. Now there’s a pattern-based design/technology co-optimization (DTCO) flow that can help define the highlighted intersection between frequently-used design styles and lithographically challenging patterns.
One of the main components of this DTCO flow, the design space explorer, finds all the possible useful patterns that can be used to identify potential lithographic problems or perform early testing for the current rule decks. However, this exposure can still be a challenge given the limited amount of internal intellectual property (IP) available to a foundry before the first customer designs are submitted.
The Layout Schema Generator (LSG) functionality embedded within the Calibre LFD™ tool is a Monte-Carlo-based process that generates “clips” of arbitrary layout patterns that comply with the targeted design rules. Each clip is created by randomly placing unit patterns in a grid, where the random placement is guided by user-defined rules and weights. The LSG tool also allows the generation of colored layouts for both double and triple patterning applications, and standard cell-like layouts with pre-defined power rail templates. These patterns and layouts can provide enough accuracy and coverage to enable useful lithographic analysis and layout verification during early design starts.
Want to learn more about the details? Check out the full explanation in our white paper, Estimating Lithographic Difficulty during Process Node Development with Calibre Design/Technology Co-Optimization.