Don’t Skip Steps: The Significance of Qualifying IP Revisions
Have you ever written a Master’s thesis, a paper for a science class, or even an article for a school magazine? If you have, you probably understand the importance of the revision process. It’s common to go back and forth, making changes and adding new content to meet the expectations of the reader, much like I did while writing this recently published article. The same goes for semiconductor IP revisions.
According to a 2023 research by Globenewswire, the semiconductor IP industry is expected to reach 11 billion USD by 2032 with a 6.7% CAGR. As a result, top semiconductor companies are investing heavily in IP production and integration flows to meet industry demands. The cost of doing so increases exponentially as they move to more advanced process technologies. Therefore, it is essential to thoroughly qualify the IP data before its release.
Semiconductor IPs are represented in various views and formats that originate from different stages of the design flow, including front-end design views represented by Verilog, VHDL, SDF, etc. as well as back-end design represented by LEF, DEF, GDS etc. and other schematic and spice views. Given this extensive range of IP data, it is crucial to qualify each format individually, as well as in relation to one another, to ensure consistency between the different views and formats.
As new features are constantly added and IPs are fine-tuned for performance gains, multiple revisions of the IP are created. To ensure that these changes in the new revisions do not introduce unexpected changes, how can we address this challenge with a solution that is less manually intensive?
If you are interested in learning more about the topic, I encourage you to read my recently published article titled “The Importance of Qualifying IP Revisions“. This article discusses why it is crucial to qualify every IP revision, the potential consequences of not performing IP revision QA, and strategies for addressing this issue.