“Interested in knowing more about Solido’s ML technologies to reduce the characterization and validation runtimes for liberty models? Check out our whitepaper “here”
Semiconductor chips are the backbone of technology, and power millions of products and innovations today. They have touched many aspects of our lives, from smart phones and laptop computers to autonomous vehicles and the high-end cloud servers, and it is hard to imagine a world without them. With the increase in demand of these technologies and electronic devices, competition in the semiconductor space is getting fierce and to be able to keep up with these demands and be successful, chipmakers are under constant pressure to not only meet the expectations of the consumers, but also create better, faster, and cheaper products.
The “better” part is taken care of by the huge investments the chipmakers make in research and development budgets today. On the other hand, getting the latest technology out in the market “faster” depends on the successful design verification to avoid manufacturing of flawed designs. The verification cycle including functional, timing, and physical verification is typically much longer at advanced technology nodes where the transistor count is very high. Therefore, it is essential that the tools and techniques used are fast and exhaustive.
While functional verification step makes sure the design conforms to its specification, timing verification is performed to optimize the performance of the design. For timing verification today, chip designers employ Static Timing Analysis (STA) tools. The basic requirement for STA tools to measure timing, power and noise accurately is the availability of accurate models of the building blocks from the standard cell libraries or the Liberty (.lib) models. Therefore, it is critical for the .libs to be as accurate as possible to reduce the verification time. At advanced technology nodes, .libs not only include complex standard cells and custom macros, but also complex data types including the advanced waveforms and the statistical variation data which are not only difficult to characterize but also very hard to validate and analyze. Traditional methods and scripts used to characterize and validate .libs have remained unchanged to a large extent. However, with shrinking technology nodes, design complexities and the need to model advanced node effects, both characterization and verification of the .libs have become increasingly difficult.
These challenges are addressed by Solido Characterization Suite from Siemens EDA. This is a solution that uses machine learning techniques to significantly speed up characterization and validation runtimes, while achieving better quality .libs .. Solido Generator uses proprietary ML techniques to accelerate the overall characterization process for additional Process, Voltage, and Temperate (PVT) corners after the initial characterization, while Solido Analytics is the advanced .lib validation and debugging solution that uses ML techniques to detect outliers and non-monotonic behaviors in the characterized data that other tools are unable to detect.
With the right tools, verification cycles can be reduced drastically. To find out more about the Solido offerings, and how it can fit into any characterization flow, refer to the white paper “Addressing library characterization and verification challenges using ML” that talks in detail about how the tools can be used to expedite and simplify the overall characterization flows without compromising on the accuracy of the .libs.