Siemens EDA at TSMC OIP 2021

Siemens EDA at TSMC OIP

Though the COVID19 pandemic swept the global economies around the world, semiconductor sales increased by 10% in 2020 fueled by demand for desktops, laptops, iPad, and smartphones, which enabled work from home and homeschooling. And as with toilet paper and sanitizer, this surge in demand disrupted the semiconductor supply chain resulting in chip shortage at a scale the world has never seen before.

To address this global semiconductor chip shortage, foundries play a pivotal role. Today TSMC dominates the production of the world’s most sophisticated ICs and has committed to overcoming the shortage by pledging to spend $100B over 3 years to expand chip capacity.

Every year, TSMC hosts an annual event Open Innovation Platform which brings together their diverse customers and partners who are instrumental in nourishing the chip design industry. This year, Siemens EDA is honored to have three Analog Mixed-Signal sessions selected in this conference. These sessions highlight various Siemens EDA solutions from Analog FastSPICE, Symphony – Mixed-Signal Platform, Solido Variation Designer, and Caliber.

Siemens EDA AMS Solutions are certified by TSMC down to 3nm FinFET, and our latest press release with TSMC shows our strong commitment to the ongoing partnership to support next-generation process technologies.

There’s a lot more going on at Siemens EDA, so be sure to stop-by our virtual booth, meet Siemens EDA Product managers and learn what is new and how we can help solve your design and verification problems.

You can attend the following sessions

#1

Machine Learning Enabled High-Sigma Verification of 5nm Standard Cell IP For high yield GPUs, HPC, automotive, and IoT applications

Authored by: Chengcheng Liu, Senior Engineer, NVIDIA Digital IP Group and Wei-Lii Tan, Senior Product Manager, AMS Verification, Siemens EDA

Track: HPC & 3DFabric

#2

Achieving first pass silicon success for High-Speed Low Power MIPI PHYs with a robust analog mixed signal verification methodology in TSMC 5nm FinFet Process

Authored by:  Eric Hong, Sr. Director of Engineering, Mixel Inc. and Sumit Vishwakarma, Product Manager, AMS Verification, Siemens EDA

Track: Mobile & Automotive

#3

Design and Verification of Clocking Macros and Sensors in N5 and N3 Processes Targeting High Performance Compute, Automotive, and IoT Applications

Authored by: Sweta Gupta, Director of Circuit Engineering, Analog Bits & Greg Curtis, Sr. Product Manager, AMS Verification, Siemens EDA

Track: Mobile & Automotive

To learn more about our solutions and how we can address you design team’s most challenging analog/mixed-signal verification challenges, please visit our AMS product page.

To register for TSMC OIP 2021 NA, please Register NOW

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